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<\/span><\/figcaption><\/figure>
New Delhi, Researchers at the Indian Institute of Technology (IIT), Guwahati have developed technology for design of fast, secure and dependable integrated circuits<\/a> (ICs) for faster and efficient computing. According to the team, the research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing<\/a> ecosystem in our country.

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.

While multi-core processors are being used in modern times, their computing power improvements continue to be insufficient, the team claimed.

\"A promising technology to improve computational efficiency is hardware accelerators<\/a>. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU<\/a> core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks,\" said Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT Guwahati<\/a>.

The team emphasised on hardware acceleration specifications that are often written in high-level languages like in C and C++ and are converted to hardware code (or register transfer level or Register−Transfer Level (RTL code), in a process called High-Level Synthesis (HLS<\/a>).

Due to the complex conversation process, HLS translation may introduce bugs in the design and, therefore, stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex.

\"We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features.\"

\"In addition to these simulators, prototypes of which are available for testing, the team has also developed a technology called HOST<\/a>, which protects Integrated Circuits from IP theft during the design cycle. It has been shown to be resilient to any known attack till date,\" he added.<\/body>","next_sibling":[{"msid":91488482,"title":"Consumer spending on mobile services set to cross pre-Jio levels in 4Q: Analysts","entity_type":"ARTICLE","link":"\/news\/consumer-spending-on-mobile-services-set-to-cross-pre-jio-levels-in-4q-analysts\/91488482","category_name":null,"category_name_seo":"telecomnews"}],"related_content":[],"msid":91488971,"entity_type":"ARTICLE","title":"IIT Guwahati develops secure Integrated Circuits for next-generation computing","synopsis":"With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.","titleseo":"telecomnews\/iit-guwahati-develops-secure-integrated-circuits-for-next-generation-computing","status":"ACTIVE","authors":[],"Alttitle":{"minfo":""},"artag":"PTI","artdate":"2022-05-11 13:54:52","lastupd":"2022-05-11 14:03:40","breadcrumbTags":["integrated circuits","devices","hls","iit guwahati","next generation computing","electronics manufacturing","cpu","multi core processors","hardware accelerators","host"],"secinfo":{"seolocation":"telecomnews\/iit-guwahati-develops-secure-integrated-circuits-for-next-generation-computing"}}" data-authors="[" "]" data-category-name="" data-category_id="" data-date="2022-05-11" data-index="article_1">

IIT古瓦哈蒂为下一代开发安全集成电路计算

随着计算的要求,有必要对特定于应用程序的处理器,可以超越当前的cpu。

  • 更新2022年5月11日02:03点坚持

新德里,印度理工学院(IIT)的研究人员,古瓦哈蒂已经开发出的技术设计快速、安全、可靠集成电路(ICs)更快更有效的计算。根据团队,研究看着自动化电子产品设计过程的所有方面像合成,对加强验证和安全性和贡献电子产品制造我国的生态系统。

随着计算的要求,有必要对特定于应用程序的处理器,可以超越当前的cpu。

同时使用多核处理器在现代,他们的计算能力改进继续不够,团队声称。

广告
“一种有希望的技术来提高计算效率硬件加速器。在硬件加速,可以将特定的任务转移到专用硬件而不是执行的CPU系统的核心。例如,可视化过程可能会转移到一个显卡,从而释放CPU执行其他任务,“说孩子叫Karfa,副教授,计算机科学与工程学系IIT古瓦哈蒂。

团队强调硬件加速规范,通常是用高级语言写的像在C和c++转换为硬件代码(或寄存器传输级(RTL代码)或注册−转移水平,在这一过程被称为高级合成(HLS)。

由于复杂的对话过程,HLS翻译可能在设计中引入了错误,因此,需要严格的验证步骤。RTL模拟器是用于验证HLS,但这些都是缓慢而复杂。

“我们已经开发出两个工具来验证HLS过程。一个是FastSim,一个快300倍的RTL模拟器比现有的商业模拟器。,另一种是DEEQ自动化C RTL等价HLS验证检查工具。没有其他工具在市场上具有相似的特性。”

“除了这些模拟器的原型,它可用于测试,团队也开发了一种技术主机,保护集成电路知识产权盗窃在设计周期。它已被证明是有弹性的任何已知的攻击,直到目前为止,”他补充道。
  • 于2022年5月11日01:54点坚持
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  • IIT古瓦哈蒂为下一代开发安全集成电路计算
\"\"
<\/span><\/figcaption><\/figure>
New Delhi, Researchers at the Indian Institute of Technology (IIT), Guwahati have developed technology for design of fast, secure and dependable integrated circuits<\/a> (ICs) for faster and efficient computing. According to the team, the research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing<\/a> ecosystem in our country.

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.

While multi-core processors are being used in modern times, their computing power improvements continue to be insufficient, the team claimed.

\"A promising technology to improve computational efficiency is hardware accelerators<\/a>. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU<\/a> core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks,\" said Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT Guwahati<\/a>.

The team emphasised on hardware acceleration specifications that are often written in high-level languages like in C and C++ and are converted to hardware code (or register transfer level or Register−Transfer Level (RTL code), in a process called High-Level Synthesis (HLS<\/a>).

Due to the complex conversation process, HLS translation may introduce bugs in the design and, therefore, stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex.

\"We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features.\"

\"In addition to these simulators, prototypes of which are available for testing, the team has also developed a technology called HOST<\/a>, which protects Integrated Circuits from IP theft during the design cycle. It has been shown to be resilient to any known attack till date,\" he added.<\/body>","next_sibling":[{"msid":91488482,"title":"Consumer spending on mobile services set to cross pre-Jio levels in 4Q: Analysts","entity_type":"ARTICLE","link":"\/news\/consumer-spending-on-mobile-services-set-to-cross-pre-jio-levels-in-4q-analysts\/91488482","category_name":null,"category_name_seo":"telecomnews"}],"related_content":[],"msid":91488971,"entity_type":"ARTICLE","title":"IIT Guwahati develops secure Integrated Circuits for next-generation computing","synopsis":"With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs.","titleseo":"telecomnews\/iit-guwahati-develops-secure-integrated-circuits-for-next-generation-computing","status":"ACTIVE","authors":[],"Alttitle":{"minfo":""},"artag":"PTI","artdate":"2022-05-11 13:54:52","lastupd":"2022-05-11 14:03:40","breadcrumbTags":["integrated circuits","devices","hls","iit guwahati","next generation computing","electronics manufacturing","cpu","multi core processors","hardware accelerators","host"],"secinfo":{"seolocation":"telecomnews\/iit-guwahati-develops-secure-integrated-circuits-for-next-generation-computing"}}" data-news_link="//www.iser-br.com/news/iit-guwahati-develops-secure-integrated-circuits-for-next-generation-computing/91488971">